1. Field of the Invention
The present invention relates to an asynchronous binary-number comparator circuit which can detect the greater or lesser of two numbers compared and possibly equality between the two numbers, and which revises its state at high speed upon any variation of the numbers under comparison, and irrespective of its previous state.
2. Discussion of the Related Art
In digital electronic systems it is very often necessary to compare two binary numbers A and B to check whether one is greater than the other (A>B or B>A) or whether they are equal.
The equality condition can easily be identified by relatively simple and fast logic circuits which use elemental logic structures.
In particular, the pairs of analogous bits of the two binary numbers can be compared separately and simultaneously with exclusive OR or XOR logic circuits; the outcomes of the comparisons between individual pairs, put into NOR logic, indicate whether the two numbers are identical or not.
If, however, it is necessary to establish which of two different numbers is the greater or the lesser, there are no elemental logic structures which can perform this operation and it is necessary to make use of complex circuits with multiple stages in cascade, which are therefore expensive and relatively slow and, in most cases, are inadequate for requirements.
In fact, whereas to identify an equality condition, as already stated, it suffices to check the equality of all of the homologous bits simultaneously, in order to identify the greater or lesser number, it is necessary to identify, from the many possible differences, the significant difference, that is, the difference of greatest weight, between homologous bits, and this requires complex circuits the limitations of which will be discussed below with reference to FIGS. 1, 2, and 3.